This invention relates to the field of semiconductor devices, and more particularly, this invention relates to a semiconductor device and process for manufacturing self-aligned contacts and landing pad structures of integrated circuits having broad applicability in memory and logic devices.
Self-aligned contact and gate formation techniques are used in integrated circuit fabrication, and are commonly used in dynamic random access memory (DRAM) and static random access memory (SRAM) processes, such as those devices used as flash memory devices. These semiconductor memory devices typically include various contact windows that often receive polysilicon or other plugs and connect cell transistor source regions to a respective storage electrode of a cell capacitor. Contact windows also connect cell transistor drain regions to respective bit lines. Often, these types of semiconductor devices include floating gate structures where data can be stored in the form of a charge on a floating gate.
The contact windows should be small dimension, and preferably smaller than the resolution limits of the exposure tools used to form the respective semiconductor devices. One common prior art contact window manufacturing technique is referred to as self-aligned contact, which often uses a window opening to a source/drain region located between word lines or gate structures. The self-aligned contact opening typically is larger in width than the space existing between word line structures. This self-aligned contact window opening, therefore, could include not only the entire width of the source/drain region, but also include some exposure of a portion of the top surface of an insulator capped, polycide gate structure, or other gate structure formed by techniques known to those skilled in the art.
Additionally, it is well known by those skilled in the art that various feature sizes and minimum space or design tolerances are maintained between semiconductor devices to maintain the electrical integrity of the semiconductor device. Any misalignment in the formation of metal contacts, for example, into a diffused region of the semiconductor device, could cause other problems in the required spacing that should exist between a contact and the surrounding device, such as a polysilicon gate. To avoid these problems created when a metal contact is misaligned, for example, between a metal contact and the gate, a landing pad is often formed between the metal contact and an underlying diffused region. The landing pad is usually formed from a doped polysilicon layer over which a silicide layer can be formed to decrease sheet resistance to tolerable levels. The landing pad usually allows for reduction in the size of the cell and tolerates greater misalignment problems.
Examples of various semiconductor devices and method of manufacturing the devices with appropriate self-aligned contacts and/or landing pads are disclosed in U.S. Pat. Nos. 5,166,771; 5,828,130; 5,866,449; 5,895,961; 5,907,779; and 5,923,988, the disclosures which are hereby incorporated by reference in their entirety.
As noted before, the self-aligned contact manufacturing process is commonly used in most common SRAM and DRAM manufacturing technologies. However, the process usually requires an additional mask and etch process to be comparable to a logic process. Two etch steps are used. A first etch step is used that has little etch selectivity of nitride over an oxide, and a second etch step is used where spacer needs must be anticipated. Thus, it was difficult to define contact window openings on top of both the polysilicon and silicon, and a self-aligned contact window opening at the same time.
It is therefore an object of the present invention to define a regular window opening and a self-aligned contact window openings at the same time, such as in a floating gate manufacturing process of a memory device.
In accordance with the present invention, a dummy landing pad can be defined and formed during a floating gate process in a polysilicon process to raise an actual polysilicon landing pad such that only one etch and resist process can be used.
In accordance with the present invention, a semiconductor integrated circuit device includes a silicon substrate having a field oxide region and spaced active region formed therein. First and second self-aligned contacts are formed in first and second self-aligned contact window openings are associated with the respective field oxide region and active region. A dummy polysilicon landing pad is formed over the field oxide region and formed below the first self-aligned contact window opening. An operative polysilicon landing pad is formed above the dummy landing pad.
In still another aspect of the present invention, the second self-aligned contact window opening comprises a first, upper portion that is formed during a first self-aligned contact etch step and a second, lower portion is formed during a second self-aligned contact etch step. The first self-aligned contact window opening is formed during the first self-aligned contact etch step. The dummy landing pad is formed during a floating gate fabrication process. A thin oxide layer is positioned below the second self-aligned contact window opening. A polysilicon landing pad overlies a portion of the active region. Sidewall spacers can be formed on the ends of the operative polysilicon landing pad.
In a method aspect of the present invention, the semiconductor integrated circuit device can be formed and comprises the step of forming a field oxide region and spaced active region within a semiconductor substrate. First and second self-aligned contact window openings are formed and associated with the respective field oxide region and active region. The method also comprises the step of forming a dummy polysilicon landing pad over the field oxide region and below the first self-aligned contact window opening. The method comprises the step of forming an operative polysilicon landing pad above the dummy landing pad.